Cache simulator assignment

In this assignment you will write and analyze MIPS assembly code, and implement a cache simulator to evaluate the effects of different caching strategies on the number of cycles required to execute a sequence of memory references. This is a pretty significant assignment, and we are giving you 2 full weeks to work on it. This is because we expect it to require 2 weeks, so plan accordingly! You might be able to find answers to these problems on the web.

Please resist the temptation to do this, and understand that turning in work that is not your original work is a violation of academic integrity. All of these problems have straightforward solutions that you should be able to work out with a bit of thought and effort.

Write a cache simulator using C programming language.

If it were a C function, it would have the following declaration:. The parameters resultvec1and vec2 are all arrays of 32 bit int values.

cache simulator assignment

The length of each array is specified by the count parameter. The computation done by the function is that for each index i in the range 0 to count-1 :.

In other words, each element of the result array should be assigned the sum of the squares of the corresponding elements of vec1 and vec2. Use the following template for your program copy these contents into a file called Problem1. Test code is provided to allow you to test your function.

cache simulation on DEV C++

Use the spim simulator to execute and debug your code. Include a comments in your code indicating. This problem focuses on simulating and evaluating caches. Regardless of which language you use, we highly encourage you to write modular, well-designed code, and to develop data types and functions to manage the complexity of the program.

Your code should compile cleanly with gcc 7. You will design and implement a cache simulator that can be used to study and compare the effectiveness of various cache configurations. Your simulator will read a memory access trace from standard input, simulate what a cache based on certain parameters would do in response to these memory access patterns, and finally produce some summary statistics to standard output. As you can see, each memory access performed by a program is recorded on a separate line.

You can ignore the third field for this assignment.

Assignment #5: Cache Lab (due on Wed Apr 08, 2020 at 11:59pm)

Your cache simulator will be configured with the following cache design parameters which are given as command-line arguments see below :. Note that certain combinations of these design parameters account for direct-mapped, set-associative, and fully associative caches:. The smallest cache you must be able to simulate has 1 set with 1 block with 4 bytes; this cache can only remember a single 4-byte memory reference and nothing else; it can therefore only be beneficial if consecutive memory references in a trace go to the exact same address.

You should probably use this tiny cache for basic sanity testing. A few reminders about the other three parameters: The write-allocate parameter determines what happens for a cache miss during a store :. Note that this parameter interacts with the following one. The write-through parameter determines whether a store always writes to memory immediately or not:. The last parameter is only relevant for associative caches: in direct-mapped caches there is no choice for which block to evict!

This would simulate a cache with sets of 4 blocks each aka a 4-way set-associative cachewith each block containing 16 bytes of memory; the cache performs write-allocate but no write-through so it does write-back insteadand it evicts the least-recently-used block if it has to.

cache simulator assignment

As an aside, note that this cache has a total size of bytes 16 kB if we ignore the space needed for tags and other meta-information.

After the simulation is complete, your cache simulator is expected to print the following summary information in exactly the format given below:. The count value is simply an occurrence count. As a concrete example, here is an example invocation of the program on one of the example traces, gcc.

Assignment 1: Cache simulation

Note that due to slight variations in how you might reasonably interpret the simulator specification, your Total cycles value could be slightly different, but should be fairly close.

Once you have that working, extend step-by-step to make the other design parameters work. Also, sanity-check your simulator frequently with simple, hand-crafted traces for which you can still derive manually what the behavior should be. More hints coming soon… Sorry, no more hints will be forthcoming on this assignment description page, but please do check out Piazza.

You should take a variety of properties into account: hit rates, miss penalties, total cache size including overheadetc.This assignment is designed to give us a better understanding about cache behavior. We will write a cache. Each line is for one memory access. First column is the address of the instruction that is causing. R W indicates the operation is a memory read write. Finally, last column is the memory. Implement a program c-sim that will simulate the operation of a cache.

Your program c-sim should support the following usage interface:. If -h is given as an argument, your program should just print out help for how a user can run the program and then quit. For this assignment: a a write-miss causes both a read and a write from the cache to the memory; b.

This makes write-through and write-back caches look alike as much as. For a write-back cache: a add a bit called the dirty bit ; b set the dirty bit when writing to a block. I can do this project with highest satisfaction! Best Regards, Szymszteinsl. Hello there, I can help you with this project.

I have enough knowledge in caching mechanisms and C language to easily complete this project. Please check out my profile for reviews on other jobs I've finished and More. I can help you in this. I have very strong c programming skills. I can provide with the best work. Hi, we have a team of technical as well as acadamic writers and do extensive data entry work for our clients, we are also working on Java and C programming extnesively, thus having the understanding of the [login to view URL] More.

I have worked on embedded system for more than 5 years and very experienced in C programming. Also I know exactly how the cache of CPU works, this task is most suitable for me. I have simulated lots of programs and projects on GCC including cache page replacement.

Please mail me the complete scenario in descriptive manner. I will ensure the quality of the simulator to the best of my knowled More. I did this exact same project as homework during my CS degree except that it is in C and supports multiple levels and cores.

I can easily modify this code and port to C or offer you the C code. The price is nego More.You will need to implement a trace-driven cache simulator, and use it to evaluate the performance of different cache architecture features.

cache simulator assignment

The project is described in detail in sim. Along with files used to make direct submissions to the submit server submit. Execution traces traces. Later you will use your cache simulator to evaluate the impact of different cache parameters, using the three application traces spice, cc, tex. Submission All your code should be in the file cache. You can submit your project directly to the submit server via its web interface here. You may also submit your project directly by executing a Java program on a computer with Java and network access.

Use the submit. You will be asked to enter your class account and password, then all files in the directory and its subdirectories will be put in a jar file and submitted to the submit server. If your submission is successful you will see the message:.

The Campus Senate has adopted a policy asking students to include the following statement on each assignment in every course: "I pledge on my honor that I have not given or received any unauthorized assistance on this assignment.

Please carefully read the academic honesty section of the course syllabus. Any evidence of impermissible cooperation on projects, use of disallowed materials or resources, or unauthorized use of computer accounts, will be submitted to the Student Honor Council, which could result in an XF for the course, or suspension or expulsion from the University.

Be sure you understand what you are and what you are not permitted to do in regards to academic integrity when it comes to project assignments. These policies apply to all students, and the Student Honor Council does not consider lack of knowledge of the policies to be a defense for violating them. Full information is found in the course syllabusplease review it at this time. Web Accessibility. Getting Started Download the following archive file p1. If your submission is successful you will see the message: Successful submission received for project 1 Academic Integrity The Campus Senate has adopted a policy asking students to include the following statement on each assignment in every course: "I pledge on my honor that I have not given or received any unauthorized assistance on this assignment.This assignment will help you understand the impact that cache memories have on performance of your C programs.

It requires you to implement several functions within the context of a program that simulates the behavior of a cache memory. The functions you need to implement focus on different areas that we have most recently studied.

In particular:. Allocation and Linked Lists : You are to implement functions that require you to allocate the proper data structures to implement the cache simulator.

You will also be required to manipulate a linked list. Knowledge from previous assignments will help here! Bit Extraction : You are to implement functions that extract bits from an address to index into the cache correctly to determine if you have a hit or a missetc. LRU : You are to implement the core of the least recently used algorithm to determine which cache line to evict when a particular set is full. You should begin by downloading the startup tar ball and copying it to your Virtual Box environment.

After you copy the archive file to your Virtual Box environment, you should execute the following command:. This will create a directory called cache-simulator that contains anumber of files and directories that you will work with.

Here is a brief summary of the files included in this assignment:. The cache-sim binary is your cache simulator and the test-sim binary is a test harness that will test various aspects of your code to determine the correctness. You are provided a framework that compiles from the beginning.

Although it compiles, it does not work yet - you must provide the implementation. You must use the Virtual Box environment or your own Linux environment to compile and run the binary files.

It is important that you compile your code in the Virtual Box environment because the representation of the trace addresses are assumed to be bit, etc. We have provided to you the solution binary so that you can see what the output is of running the cache simulator. To try it out you can run the following:. The cache-sim-soln program takes four arguments identical to cache-sim.

If you run the solution without the arguments you will see a usage print out:. You must provide the number of bits used to identify the set, the associativity of the cache number of lines per setthe number of bits to identify the byte within a block, and the trace file to run the cache simulator on. The assignment requires you to complete the implementation of a cache simulator. You can test your cache simulator on trace files that we provide. We will first describe the trace files and then explain the parts that you must implement.

The assignment requires you to implement a cache simulator that will read in an address trace of running an actual program.

We have generated these trace files using valgrind.By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service. The dark mode beta is finally here.

Change your preferences any time. Stack Overflow for Teams is a private, secure spot for you and your coworkers to find and share information. Ok this is only my second question, and it's quite a doozy. It's for a school assignment, but no one including the TAs seems to be able to help me. It's kind of a tall order but I'm not sure where else to turn. Essentially the assignment was to make a cache simulator. This version is direct mapping and is actually only a small portion of the whole project, but if I can't even get this down I have no chance with other associativities.

I'm posting my whole code because I don't want to make any assumptions about where the problem is. If anyone could at least point me in the right direction it would be greatly appreciated. I've been stuck on this for about 12 hours. You've got two problems. Firstly, Scott Wales is correct about your hex2bin function - you have a 'x' where you mean '4'. Secondly, you are not correctly counting a cache miss when you hit an invalid cache slot.

You can simply handle "invalid" with exactly the same code path you use for a miss:. Learn more. Cache Simulator in C Ask Question. Asked 9 years, 11 months ago. Active 7 years, 3 months ago. Viewed 25k times. Bill the Lizard k gold badges silver badges bronze badges. DuffDuff DuffDuff 1 1 gold badge 1 1 silver badge 6 6 bronze badges. PS: I tried so hard to make this readable according to the formatting here.

Sorry if it still makes your eyes bleed! Just because your TA can't figure it out doesn't mean the answer is totally beyond your capabilities.

He may know the subject matter better than you, but you know your code better than he does, and you need to learn to figure out what's wrong on your own. That's just a "Replace all" error from how many times I've altered that function. Ken Bloom I mean my TAs won't even look at the code. Nothing against them: they have their own projects and finals to work on. I was just mentioning that to show that I have tried to go to people in my class.

I've gone through it manually with small tracefiles and it works correctly but I cannot do that with a file that is thousands of lines long and that is where the problem occurs. Active Oldest Votes. You can simply handle "invalid" with exactly the same code path you use for a miss: if newCache[totalset].

cache simulator assignment

Wow thanks. I had originally been adding my misses that way but since they were too high to start with I reduced them by removing that code. I can't believe this was almost all because of that stupid 'x'.GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together. If nothing happens, download GitHub Desktop and try again. If nothing happens, download Xcode and try again.

If nothing happens, download the GitHub extension for Visual Studio and try again. The cache simulator first reads in inputs from the command line from the user. After it checks to see if all of the inputs are valid, it then goes and starts reading from the file. After checking the inputs, the simulator finds the number of sets, lines, bits needed for the set index, and bits needed for the block offset. These functions are where everything is implemented and the number of cache hits and misses, memory reads and writes are incremented.

Since this is the bulk of the logic, these will be explained later on below. It calculates this by subtracting the number of bits needed for the set index and the number of bits needed for the block offset from the length of the binary address. This uses the bits of the address between the tag and the block offset to calculate the set number. The simulator takes these bits and translates them into decimal and then returns it as the index.

This allows the simulator to later find out which line was last used in order to figure out which line to evict. Now, back to the write-through implementation. First, it checks the set for a line where the tags match. This will give us a cache hit if there is a match. It then writes the data into the line and then into lower memory, giving us a memory write.

If there is no cache hit, we get cache miss and a memory read, and it looks through the set for a line that is empty not valid. If it finds an empty cache line, it then writes data into the line and then into lower memory, giving us a memory write.

If there is no empty cache line, then it looks to evict the last used line in the set, writing data into the line and then into lower memory, giving us a memory write. With this implementation, there will always be a memory write. This will give us a cache hit if there is a match and then returns the data.By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service. The dark mode beta is finally here. Change your preferences any time.

Stack Overflow for Teams is a private, secure spot for you and your coworkers to find and share information. Ok this is only my second question, and it's quite a doozy. It's for a school assignment, but no one including the TAs seems to be able to help me. It's kind of a tall order but I'm not sure where else to turn. Essentially the assignment was to make a cache simulator. This version is direct mapping and is actually only a small portion of the whole project, but if I can't even get this down I have no chance with other associativities.

I'm posting my whole code because I don't want to make any assumptions about where the problem is. If anyone could at least point me in the right direction it would be greatly appreciated. I've been stuck on this for about 12 hours.

You've got two problems. Firstly, Scott Wales is correct about your hex2bin function - you have a 'x' where you mean '4'. Secondly, you are not correctly counting a cache miss when you hit an invalid cache slot. You can simply handle "invalid" with exactly the same code path you use for a miss:. Learn more. Cache Simulator in C Ask Question. Asked 9 years, 11 months ago. Active 7 years, 3 months ago.


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